The invention relates to a solid state image pick-up device.
In the past, the solid state image pick-up devices have been widely used which comprise charge transfer devices such as CCD, etc. or MOS transistors. However, these image pick-up devices have some drawbacks such as a leakage of charge during a charge transferring operation, a low optical detection sensitivity and packing density, etc. Then, in order to solve all these drawbacks a solid state image pick-up device has been proposed which comprises static induction transistors (SITs). For example, Japanese Patent Laid-Open No. 55-15,229 discloses an image pick-up device of this type which comprises a large number of SITs arranged in a matrix, the gates of the SITs in each row being connected to a corresponding row line, the drains of the SITs in each column being connected to a corresponding column line and the sources of SITs in each row are connected to a corresponding clear line. Further, an improved device of this type has been proposed which comprises a capacitor connected to the gate of each SIT. FIGS. 1A and 1B are a sectional view and a top plan view of the SITs in such a known solid state image pick-up device, respectively.
In this know solid state image pick-up device, an n.sup.+ -type buried layer 2 forming the source region of the SIT is formed between a p-type substrate and an n-type epitaxial layer 3 deposited thereon, in a surface of which epitaxial layer an n.sup.+ drain region 4 and a p.sup.+ gate region 5 are formed by means of a thermal diffusion process. In order to effectively control the channel region between the source and drain regions 2 and 4 by means of the gate region 5, the diffusion depth of the drain region 4 is smaller than that of the gate region 5. On the drain region 4 is provided a drain electrode 6 and on the gate region 5 is provided a gate electrode 8 via an insulating layer 7 to form a so-called MIS gate structure which constitutes a gate capacitor. The adjacent SITs are isolated from each other by an insulating region 9 formed between them.
In such a device, it the gate region 5 is reverse biased with respect to the source region 2, in absence of optical input the channel region is depleted so that no drain current flows even when a forward bias is applied between the source and the drain. In this condition, if hole-electron pairs are then generated in the channel region by the optical input, the electrons thus generated are stored or drained by the drain region 4, while the holes are stored in the gate region 5 and charge the gate capacitor of the MIS gate structure to raise the gate potential by .DELTA.V.sub.G. When it is assumed that a sum of the capacitance of the gate capacitor and the capacitance of the depletion layer in the channel region is C.sub.G and the amount of charges generated by the optical input and stored in the gate region is Q.sub.L, it holds that .DELTA.V.sub.G =Q.sub.L /C.sub.G. If a readout pulse .phi..sub.G is applied to the gate electrode 8 after a certain storage time, the gate potential becomes .phi..sub.G +.DELTA.V.sub. G and thus the reverse bias potential between the gate and drain regions 5 and 4 is decreased, so that the depletion layer is reduced to flow a drain current corresponding to the optical input between the source and the drain. This drain current corresponds to .DELTA.V.sub.G amplified by the amplification factor of the SIT and thus has a large amplitude. It is noted that if the source and the drain of the SIT shown in FIG. 1 are exchanged with each other a similar operation may be obtained.
FIG. 2A shows a circuit arrangement of the solid state image pick-up device comprising the above described SITs arranged in a matrix and each forming a picture cell and FIG. 2B shows signal waveforms for illustrating the operation thereof. In this circuit arrangement, each SIT 10-1, 10-2, . . . is a normal-off type p-channel SIT described above and the output video signal corresponding to the optical input may be derived by means of X-Y address system. For this purpose, the sources of the SITs in each row are connected to a common source line 11-1, 11-2, . . . , to which lines are selectively applied a bias voltage V.sub.s and the gates of the SITs in each X-row are connected through a corresponding row line 12-1, 12-2, . . . to a vertical selection shift register 13. Further, the drains of the SITs in each Y-column are connected to a corresponding column line 14-1, 14-2, . . . , these column lines being connected to a video line 17 through corresponding horizontal selection transistors 16-1, 16-2, . . . , respectively which transistors are selectively driven by a horizontal selection shift register 15. To the video line 17 is applied a video voltage V.sub.o through a load resistor 18.
Now, the readout operation of one (for example SIT 10-1) of the SITs is considered. At first, it is assumed that the bias voltage V.sub.s which is applied to the source lines 11-1, 11-2, . . . is established at a suitable value, for example, zero volt and a row selection pulse .phi..sub.G1 is applied from the vertical selection shift register 13 to the low line 12-1. In this condition, when a readout pulse .phi..sub.D1 is then supplied from the horizontal selection shift register 15 to the horizontal selection transistor 16-1, the SIT 10-1 is selected and this SIT flows a drain current through the load resistor 18, the video line 17, the horizontal selection transistor 16-1 and the column line 14-1 to produce an output voltage V.sub.out at an output terminal 19. As described above, this drain current is a function of the gate voltage which is a function of the optical input, so that the increment .DELTA.V.sub.out of the output voltage from the dark voltage corresponds to the optical input. That is, this voltage .DELTA.V.sub.out corresponds to .DELTA.V.sub.G amplified by the amplification factor of SIT and thus has a large amplitude. Subsequently, a readout pulse .phi..sub.D2 is applied from the horizontal shift register 15 to the horizontal selection transistor 16-2 to read out the SIT-2 and so on. After the readout of all the SITs in this row has been completed, a next row selection pulse .phi..sub.G2 is applied from the vertical selection shift register 13 to the next row line 12-2, during the duration of which pulse the outputs of the SITs in this row may be successively read out in the manner as described above.
In the solid state image pick-up device described above, the gate potentials of the SITs may be reset in two different ways--that is, a negative going pulse is applied as the bias voltage V.sub.s to each source line 11-1, 11-2, . . . to forward bias the p-n junction between the gates and sources of the SITs in each row, or the row selection pulse applied to the gates of the SIT in each row is selected in suitably large amplitude and long duration so that each SIT in the row may be reset simultaneously with the readout thereof. However, the first reset method has a drawback that the signal charge integration periods of the respective SITs in a row are different from each other, because the SITs are reset in each row. The second reset method is unstable in operation which is undesirable in practical use and also has the same drawback of the first method.